A FAST TUNING HF DDS SYNTHESIZER

IMPORTANT- PLEASE READ

This project was conceived in the late 90's when the 4MHz 16F84 was the most widely, and easily available Flash PIC processor. The aim was to produce a DDS controller with minimum hardware, that would offer a good linear tuning rate at 10Hz steps. At that time many designs employed variable rate tuning to provide usable tuning speeds with 4MHz PIC's and LCD modules. I wanted to produce a system that used linear tuning steps, with a high resolution encoder, to emulate the feel of a real VFO.  This dual PIC approach achieved this by dividing tasks between two processors. The time critical routines associated with the tuning process were placed in one processor and the less critical conversion and display routines in the second. A serial interface was used to transfer data between the two processors. The finished design was used in a transceiver for over a year before being replaced by a 16F877 design. In it's current form there is scope for further improvement, notably in reducing data transfer time of the serial interface (by making it asynchronous?) and perhaps by reducing the refresh rate of the display data, (rather than transfer data upon the LCD becoming free, update every, say, 10 passes of the main tuning loop).

Unfortunately, this website article and a short description published in RadComs' Technical Topics column caused considerable controversy and even attracted some severe criticism. Even now there is still misunderstanding surrounding the background and objectives for the project. Some interpreted it as a suggestion that PIC's were too slow and hence not suited to DDS controller applications. This was and is certainly not the case! At that time the use of multiple processors, whilst common in industry, was a rarity in Amateur Radio. Through this project I wanted to draw attention to a technique that could offer a simple and flexible solution for real time applications. 

In a few years much has changed, newer processors offer much higher clock rates and many hardware and instruction set improvements over the venerable 16F84. Even during the development of the project 10MHz variants of the 16F84 became available offering a significant  improvement in program execution time. 

So, is the dual PIC approach still valid for DDS controller project? Probably not, but as a technique it remains very powerful and perhaps may find application elsewhere. On this basis I leave the article posted for reference.

Best Regards

Ron Taylor September 2004

Introduction

One of the problems facing designers of multi band HF transceivers has been the design of a stable local oscillator system capable of spanning over 4 octaves. Traditionally the frequency span problem has been overcome by using heterodyning, multiple phase locked oscillators or PLL synthesizers combined with high frequency 1st IF's. An exiting new technology is now becoming available to amateur experimenters using a technique called Direct Digital Synthesis (DDS). This approach constructs a sine wave from a waveform description held in a digital table and outputs it as a continuous wave at a rate set by the fractional division of a reference clock. The fractional divider and waveform generator circuitry all all contained in a single device together with interface circuitry for frequency programming and low power RF buffer amplifiers.

The project shown on the following pages uses an AD 9850BRS from analog devices, an industry standard two line LCD display, two 16F84 PIC processors to manage the DDS and display, an optical shaft encoder and a pair of MMIC amplifiers to generate up to +10dBm to drive a diode ring mixer.

Those with a thirst for more knowledge on DDS techniques and devices are referred to www.analog.com for products, specifications, data sheets and applications.

Here's some basic information;

Noise

The DDS output spectrum contains quantisation noise at around -80dBc for a (12 bit A to D) and the occasional spur. The quantisation noise is a function of the A to D resolution, the more bits the lower the noise - in theory a 6dB improvement for each A to D bit. The AD 9850 is a 12 bit device, 14 bit devices are becoming available these will offer an improved noise floor. The only way to avoid the spurs produced by the current DDS devices is either use the devices in a narrow band designed to be clear of spurs or to phase lock a "clean up VCO". However, if you are prepared to accept the odd "bleep" sweeping through your tuning range - usually backwards at a much faster rate, then spurs are not a problem. To prevent quantisation noise from de-sensitizing your receiver system it is important to use a good balanced mixer for a front end. With the synthesizer shown and the Belthorn SSB IF Module sensitivity at 14MHz has been measured at 0.3uV for an estimated 10dB SNR, with no preselector filtering or amplification.

Phase noise is almost entirely a function of the reference oscillator, the DDS contribution is minimal. In practice packaged HCMOS oscillator is suitable - and simple. For optimum results you may consider a discrete crystal oscillator.

Programming and Frequency

Frequency data is passed to the device as a 32 bit serial stream at TTL levels. The interface on the AD9850 can operate at 10Mb/s. The frequency resolution of the AD9850 is a function of clock rate. The device will clock at up to 125MHz. The fractional divider offer 2³² (4,294,967,296 ) division rates, the DDS output frequency is set by

F out = (frequency word / 2³²) x Fclock

For a 125MHz clock the minimum tuning step is 125MHz / 2³² = 0.0291 Hz

 In practice a more convenient step rate of 1, 10 or 100Hz is used in local oscillator systems.

CIRCUIT DESCRIPTION

After building and using an AD9850 DDS synthesizer based upon information from several DDS and PIC projects I very quickly came to appreciate one of the chief limitations of the single PIC control system, particularly when used in synthesizer employing a "slow" LCD frequency display.

I rebuilt the synthesizer exchanging my home made 32 step ex-PC mouse shaft encoder for a reasonably priced 512 step HP-Agilent HEDS 9100 encoder from Farnell. I adapted a fine piece of software, jointly developed by Curtis W. Preuss WB2V, Bruce Stough AA0ED and Craig Johnson AA0ZZ and published as "siggen3a" on the PIC resources section of the NJ-QRP Web site, http://www.njqrp.org . This software was designed to operate on a single PIC DDS system for use as a signal generator or local oscillator for direct conversion transceivers. The very logical program structure and highly comprehensive line documentation was a real benefit. Having never programmed PIC’s before I used this program as a combined tutorial and a crash course in 16F84 programming! First I modified the LCD routines slightly to make them compatible with my display. Next I added an IF offset routine to adapt the system for use with my Belthorn SSB IF Module. Once I had checked that the software worked in a single PIC system I then took the bold step of splitting the software into two programs each running on a 16F84 -10 PIC, one to scan the controls and manage the DDS and the other to convert binary frequency data into ASCII and manage the LCD display. A simple asynchronous serial interface allows the two PIC’s to communicate with each other and allows each PIC to be run at different clock rates.

This technique could also be applied to conventional serial programmed PLL synthesizers, perhaps using a varicap crystal oscillator for interpolation in the conversion loop and main PLL step size of 10kHz to keep the loop tuning rate high.